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rev.1.00, mar.12.2004, page 1 of 11 r1rw0404d series 4m high speed sram (1-mword 4-bit) rej03c0115-0100z rev. 1.00 mar.12.2004 description the r1rw0404d is a 4-mbit high speed static ram organized 1-mword 4-bit. it has realized high speed access time by employing cmos process (6-transistor memory cell) and high speed circuit designing technology. it is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. the r1rw0404d is packaged in 400-mil 32-pin soj for high density surface mounting. features ? single supply: 3.3 v 0.3 v ? access time: 12 ns (max) ? completely static memory ? no clock or timing strobe required ? equal access and cycle times ? directly ttl compatible ? all inputs and outputs ? operating current: 100 ma (max) ? ttl standby current: 40 ma (max) ? cmos standby current : 5 ma (max) : 0.8 ma (max) (l-version) ? data retention current: 0.4 ma (max) (l-version) ? data retention voltage: 2 v (min) (l-version) ? center v cc and v ss type pin out
r1rw0404d series rev.1.00, mar.12.2004, page 2 of 11 ordering information type no. access time package R1RW0404DGE-2PR 12 ns 400-mil 32-pin plastic soj (32p0k) r1rw0404dge-2lr 12 ns pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 a4 cs# i/o1 v cc v ss i/o2 we# a5 a6 a7 a8 a9 a19 a18 a17 a16 a15 oe# i/o4 v ss v cc i/o3 a14 a13 a12 a11 a10 nc (top view) 32-pin soj pin description pin name function a0 to a19 address input i/o1 to i/o4 data input/output cs# chip select oe# output enable we# write enable v cc power supply v ss ground nc no connection
r1rw0404d series rev.1.00, mar.12.2004, page 3 of 11 block diagram i/o1 . . . i/o4 we# input data control column i/o column decoder 1024-row 64-column 16-block 4-bit (4,194,304 bits) row decoder oe# cs# cs cs v cc v ss cs a14 a13 a12 a5 a6 a7 a11 a10 a3 a1 a8 a9 a19 a17 a18 a15 a0 a2 a4 a16 (lsb) (msb) (lsb) (msb)
r1rw0404d series rev.1.00, mar.12.2004, page 4 of 11 operation table cs# oe# we# mode v cc current i/o ref. cycle h standby i sb , i sb1 high-z ? l h h output disable i cc high-z ? l l h read i cc d out read cycle (1) to (3) l h l write i cc d in write cycle (1) l l l write i cc d in write cycle (2) note: h: v ih , l: v il , : v ih or v il absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.5 to +4.6 v voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.5 * 2 v power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ? 55 to +125 c storage temperature under bias tbias ? 10 to +85 c notes: 1. v t (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v t (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns. recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit supply voltage v cc * 3 3.0 3.3 3.6 v v ss * 4 0 0 0 v input voltage v ih 2.0 ? v cc + 0.5 * 2 v v il ? 0.5 * 1 ? 0.8 v notes: 1. v il (min) = ? 2.0 v for pulse width (under shoot) 6 ns. 2. v ih (max) = v cc + 2.0 v for pulse width (over shoot) 6 ns. 3. the supply voltage with all v cc pins must be on the same level. 4. the supply voltage with all v ss pins must be on the same level.
r1rw0404d series rev.1.00, mar.12.2004, page 5 of 11 dc characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) parameter symbol min max unit test conditions input leakage current ii li i ? 2 a v in = v ss to v cc output leakage current ii lo i ? 2 a v in = v ss to v cc operation power supply current i cc ? 100 ma min cycle cs# = v il , l out = 0 ma other inputs = v ih /v il standby power supply current i sb ? 40 ma min cycle, cs# = v ih , other inputs = v ih /v il i sb1 ? 5 ma f = 0 mhz v cc cs# v cc ? 0.2 v, (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v ? * 1 0.8 * 1 output voltage v ol ? 0.4 v i ol = 8 ma v oh 2.4 ? v i oh = ? 4 ma note: 1. this characteristics is guaranteed only for l-version. capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min max unit test conditions input capacitance * 1 c in ? 6 pf v in = 0 v input/output capacitance * 1 c i/o ? 8 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
r1rw0404d series rev.1.00, mar.12.2004, page 6 of 11 ac characteristics (ta = 0 to +70 c, v cc = 3.3 v 0.3 v, unless otherwise noted.) test conditions ? input pulse levels: 3.0 v/0.0 v ? input rise and fall time: 3 ns ? input and output timing reference levels: 1.5 v ? output load: see figures (including scope and jig) d out 353 ? 319 ? 3.3 v 5 pf output load (b) (for t clz , t olz , t chz , t ohz , t whz , and t ow ) output load (a) 1.5 v 30 pf d out rl=50 ? zo=50 ? read cycle r1rw0404d -2 parameter symbol min max unit notes read cycle time t rc 12 ? ns address access time t aa ? 12 ns chip select access time t acs ? 12 ns output enable to output valid t oe ? 6 ns output hold from address change t oh 3 ? ns chip select to output in low-z t clz 3 ? ns 1 output enable to output in low-z t olz 0 ? ns 1 chip deselect to output in high-z t chz ? 6 ns 1 output disable to output in high-z t ohz ? 6 ns 1
r1rw0404d series rev.1.00, mar.12.2004, page 7 of 11 write cycle r1rw0404d -2 parameter symbol min max unit notes write cycle time t wc 12 ? ns address valid to end of write t aw 8 ? ns chip select to end of write t cw 8 ? ns 9 write pulse width t wp 8 ? ns 8 address setup time t as 0 ? ns 6 write recovery time t wr 0 ? ns 7 data to write time overlap t dw 6 ? ns data hold from write time t dh 0 ? ns write disable to output in low-z t ow 3 ? ns 1 output disable to output in high-z t ohz ? 6 ns 1 write enable to output in high-z t whz ? 6 ns 1 notes: 1. transition is measured 200 mv from steady voltage with output load (b). this parameter is sampled and not 100% tested. 2. address should be valid prior to or coincident with cs# transition low. 3. we# and/or cs# must be high during address transition time. 4. if cs# and oe# are low during this period, i/o pins are in the output state. then, the data input signals of opposite phase to the outputs must not be applied to them. 5. if the cs# low transition occurs simultaneously with the we# low transition or after the we# transition, output remains a high impedance state. 6. t as is measured from the latest address transition to the later of cs# or we# going low. 7. t wr is measured from the earlier of cs# or we# going high to the first address transition. 8. a write occurs during the overlap of a low cs# and a low we#. a write begins at the latest transition among cs# going low and we# going low. a write ends at the earliest transition among cs# going high and we# going high. t wp is measured from the beginning of write to the end of write. 9. t cw is measured from the later of cs# going low to the end of write.
r1rw0404d series rev.1.00, mar.12.2004, page 8 of 11 timing waveforms read timing waveform (1) (we# = v ih ) t aa t acs t rc t oe t clz valid data address cs# d out valid address high impedance t ohz oe# t oh t chz t olz read timing waveform (2) (we# = v ih , cs# = v il , oe# = v il ) t aa t rc valid data address d out valid address t oh t oh
r1rw0404d series rev.1.00, mar.12.2004, page 9 of 11 read timing waveform (3) (we# = v ih , cs# = v il , oe# = v il )* 2 valid data cs# d out high impedance high impedance t clz t acs t rc t chz write timing waveform (1) (we# controlled) address we#* 3 d out d in t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs#* 3 t ohz * 4 * 4 oe# high impedance* 5
r1rw0404d series rev.1.00, mar.12.2004, page 10 of 11 write timing waveform (2) (cs# controlled) address we# * 3 d out d in t wc t wp t wr t cw t dw t dh valid address t aw valid data t as cs# * 3 t whz t ow * 4 * 4 high impedance* 5
r1rw0404d series rev.1.00, mar.12.2004, page 11 of 11 low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for l-version. parameter symbol min max unit test conditions v cc for data retention v dr 2.0 ? v v cc cs# v cc ? 0.2 v (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v data retention current i ccdr ? 400 a v cc = 3 v, v cc cs# v cc ? 0.2 v (1) 0 v v in 0.2 v or (2) v cc v in v cc ? 0.2 v chip deselect to data retention time t cdr 0 ? ns see retention waveform operation recovery time t r 5 ? ms low v cc data retention timing waveform cc v 3.0 v 0 v cs# t cdr t r v cc cs# v cc ? 0.2 v 2.0 v dr v data retention mode
revision history r1rw0404d series data sheet contents of modification rev. date page description 0.01 oct. 01, 2003 ? initial issue 1.00 mar.12.2004 ? deletion of preliminary
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